Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode structure that overlies the channel. The ICs are usually formed using both P-channel FETs (PMOS transistors or PFETs) and N-channel FETs (NMOS transistors or NFETs) and the IC is then referred to as a complementary MOS or CMOS circuit. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, increasing transistor density and thus decreasing transistor size has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
As advanced metal-oxide-semiconductor (MOS) technology continues to scale and move into the deep-sub-micron geometry dimensions, the optimization of source/drain regions has become complex. Conventional techniques that are employed to form the source/drain regions can negatively impact the active areas and the gate electrode structures. In particular, epitaxially-grown semiconductor regions are generally formed adjacent to the channels beneath the gate electrode structures, in recesses that are formed between a shallow trench isolation structure and the gate electrode structures. For example, epitaxially-grown silicon germanium applies a compressive longitudinal stress to the channel, and such stress has been found to increase mobility of electrons in the channel of a PMOS transistor. Conversely, epitaxially-grown carbon-doped silicon applies a tensile longitudinal stress to the channel, and such stress has been found to increase mobility of electrons in the channel of an NMOS transistor. Source/drain regions are formed in the epitaxially-grown semiconductor regions after formation thereof. However, many semiconductor materials that are generally employed to form the epitaxially-grown semiconductor regions propagate through both lateral and vertical growth. For example, epitaxially-grown silicon germanium having from 30 to 40 weight % germanium, based on the total weight of the epitaxially-grown silicon germanium, is generally employed due to excellent controllability and quality of the resulting epitaxially-grown semiconductor regions, although such epitaxially-grown silicon germanium propagates through both lateral and vertical growth. Because the shallow trench isolations structures generally have a surface on an equal or recessed plane relative to a final surface of the epitaxially-grown semiconductor regions, facet overgrowth may occur over an edge of the shallow trench isolation structure during formation of the epitaxially-grown semiconductor regions. The facet overgrowth may cause undesirable shorting between subsequently-formed electrical interconnects and the source/drain regions. While epitaxially-grown silicon germanium that includes higher amounts of germanium, such as at least 50 weight % germanium, exhibits less lateral propagation than epitaxially-grown silicon germanium having from 30 to 40 weight % germanium, epitaxially-grown silicon germanium having at least 50 weight % germanium exhibits inferior quality of the resulting epitaxially-grown semiconductor regions and is more difficult to control than epitaxially-grown silicon germanium having from 30 to 40 weight % germanium.
Accordingly, it is desirable to provide methods of forming integrated circuits with minimized facet overgrowth of epitaxially-grown semiconductor regions over the shallow trench isolation structures. It is also desirable to minimize the facet overgrowth while maintaining the quality of the resulting epitaxially-grown semiconductor regions and controllability of epitaxially-grown semiconductor region formation. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.